1. Field of the Invention
The inventive concept relates to a stack package, and a semiconductor package including the stack package, and more particularly, to a stack package including a supporter attached onto a first semiconductor chip on which a second semiconductor chip is stacked, and a semiconductor package including the stack package.
2. Description of the Related Art
Along with the developments of high-speed and highly-integrated semiconductor devices, methods to connect semiconductor chips in a semiconductor package have been developed. Such methods include a conventional wire bonding method, a package-on-package (PoP) method, and a system-in-package (SIP) method in which semiconductor chips are directly connected to each other through micro bumps. Specifically, as the number of input/output pins has remarkably increased along with the developments of highly-integrated semiconductor devices, technologies to connect semiconductor chips by using a through silicon via (TSV) with fine pitches have been widely developed, and a semiconductor stack structure has been applied to a general-purpose field by using these technologies.
In semiconductor chip stack technologies, thin semiconductor chips are stacked on one another. However, since the rigidity of silicon (Si) is weak, warpage may be seriously caused due to a difference in the coefficients of thermal expansion (CTE) of a semiconductor chip and a molding member.